Our Current Research Thrusts:
In the midst of data revolution, peta bytes of data being generated every hour, data deluge has placed an unprecedented demand on storage systems to be ultra-reliable, affordable and resource-efficient.

Below are short descriptions of a selection of our recent research work:

Binary and Non-Binary LDPC Codes applied to
 Data Storage Systems
Behzad Amiri and Lara Dolecek

Non-binary low-density parity-check (LDPC) codes have recently drawn remarkable attention due to their  superior performance compared to their binary counterparts. Non-binary LDPC codes use message passing (MP) decoders due to the high computational complexity of the optimal maximum likelihood decoders. It  has been shown that under MP decoding, certain non-codewords are vying with codewords to be the output of the decoder. The presence of these non-codewords can significantly undermine the performance of MP decoded LDPC codes. These non-codewords specifically result in an undesirable change in the slope of the error rate curves in high signal-to-noise ratio (SNR) region; a phenomenon which is called the error floor. For binary LDPC codes, the origin of this performance degradation is well-known and often attributed to the so-called absorbing sets. The focus of this work is to provide a general framework to analyze the undesirable absorbing sets over non-binary alphabets. In light of this analysis, we offer design guidelines for finite-length non-binary codes free of absorbing sets of small size. These guidelines demonstrate that even under the preserved topology, the performance of non-binary graph-based codes can be substantially improved by manipulating edge weights to avoid small absorbing sets. Our simulation results show that the proposed method offers more than one order of magnitude performance improvement for non-binary LDPC codes in the error floor region. These results can potentially impact a broad range of data storage and communication technologies that need to operate in high-reliability regions.

Dynamic Voltage Allocation Based on Mutual Information For NAND Flash Memory
Adam Williamson, Tsung-Yi Chen, Kasra Vakilinia, Tong Zhang, and Rick Wesel


Degradation in Flash memory depends on the total charge written and erased, rather than simply the number of program/erase cycles. Using this model, we introduce an algorithm that maintains constant information-theoretic storage capacity (the storage available in the Flash memory given the current level of degradation) by gradually increasing the program-voltage levels over time. We provide a numerical example in which the dynamic charge level algorithm increases lifetime by 80%.

Soft Information for LDPC Decoding in Flash: Mutual-Information Optimized Quantization
Jiadong Wang, Tom Courtade, and Rick Wesel


The increased density of high-capacity NAND Flash memory also increases the raw bit error rate (BER), making powerful error correction coding necessary. Traditional Flash memories employ simple algebraic codes, such as BCH codes, that can correct a fixed, specified number of errors. Our work investigates the application of low density parity-check (LDPC) codes which are well known for their ability to approach capacity in the additive white Gaussian noise (AWGN) channel. We obtain soft information for the LDPC decoder by performing multiple cell reads with distinct word-line voltages. The values of the word-line voltages (also called reference voltages) are optimized by maximizing the mutual information between the input and output of the multiple-read channel. Our results show that using this soft information in the LDPC decoder provides a significant benefit and enables the LDPC code to outperform a BCH code with comparable rate and block length over a range of block error rates.

Graded Bit-Error Correcting Codes for Flash Memories
Ryan Gabrys, Eitan Yaakobi, and Lara Dolecek


Supported by empirical data collected from a TLC (triple-level cell) Flash memory device, we have developed a class of codes that exploits the asymmetric nature of the error patterns in Flash devices by using tensor product operations. We call these codes graded bit-error-correcting codes. As demonstrated on the data collected from a Flash chip, these codes significantly delay the onset of errors and therefore have the potential to prolong the lifetime of the memory devices.

Dynamic Threshold Schemes For Multi-level Memories

Frederic Sala, Ryan Gabrys, and Lara Dolecek


In NVMs (non-volatile memories), reading stored data is typically done through the use of fixed thresholds. However, due to voltage drift and other physical effects due to the nature of the devices comprising NVMs, this approach results in significant errors. To combat this problem, the notion of dynamic thresholding was recently introduced. In our work, we show how to apply the idea of dynamic thresholds to multi-level cell (MLC) memories. The scheme we introduce has improved performance over fixed thresholds and can be combined with various flavors of error correction codes.